Fault-Tolerant Sorting Networks

This thesis studies sorting circuits, networks, and PRAM algorithms that are tolerant to faults. We consider both worst-case and random fault models, although we mainly focus on the more challenging problem of random faults. In the random fault model, the circuit, network, or algorithm is required to sort all n-input permutations with probability at least 1 -1 even if the result of each comparison is independently faulty n with probability upper bounded by a fixed constant. In particular, * we construct a passive-fault-tolerant sorting circuit with O(n log n log log n) comparators, thereby answering an open question posed by Yao and Yao in 1985, * we construct a reversal-fault-tolerant sorting network with O(n log g 2 3 n) comparators, thereby answering an open question posed by Assaf and Upfal in 1990, * we design an optimal O(log n)-step O(n)-processor deterministic EREW PRAM fault-tolerant sorting algorithm, thereby answering an open question posed by Feige, Peleg, Raghavan, and Upfal in 1990, and * we prove a tight lower bound of Q(nlog 2 n) on the number of comparators needed for any destructive-fault-tolerant sorting or merging network, thereby answering an open question posed by Assaf and Upfal in 1990. All the upper bound results are based on a new analysis of the AKS sorting circuit, which is of interest in its own right. Previously, the AKS sorting circuit was not believed to be fault-tolerant because the expansion properties that were believed to be crucial for the performance of the circuit are destroyed by random faults. The new analysis of the AKS sorting circuit uses a much weaker notion of expansion that can be preserved in the presence of faults. All previous fault-tolerant sorting circuits, networks, and parallel algorithms used O(log2 n) depth and/or (n log2 n) comparisons to sort n numbers, and no nontrivial lower bounds were known. Finally, we use simulation methods to construct practical circuits of small depth that sort most permutations. Simulation results show that such circuits have depth smaller than Batcher's classic circuits and that they are tolerant to a large number of faults. Thesis Supervisor: Tom Leighton Title: Professor of Applied Mathematics